Exemplary embodiments of the present invention relate to a delay circuit for delaying an input signal and a method for driving the same.
A delay circuit refers to a circuit which delays an input signal in order to match signal timing. In particular, a variable delay circuit refers to a circuit which delays an input signal according to a set value. Since a variety of semiconductor devices must be operated based on their inherent operation orders and in synchronization with a variety of operation timings, variable delay circuits are widely applied to semiconductor devices.
FIG. 1 is a block diagram of a conventional delay circuit for delaying an input signal according to a set delay value.
Referring to FIG. 1, the conventional delay circuit includes a plurality of shift units 101 to 104 coupled in series, and a selection unit 120 configured to select one of a plurality of output signals FF1 to FFi of the shift units 101 to 104. Here, the ‘i’ in FFi represents a variable integer.
The shift units 101 to 104 coupled in series delay their input signals by 1 clock, and the selection unit 120 selects one of the output signals FF1 to FF1 of the shift units 101 to 104, and outputs the selected output signal as a final output signal OUT of the delay circuit. Therefore, the delay value of the delay circuit changes according to the output signal of the shift unit selected by the selection unit 120.
The selection unit 120 selects one of the output signals of the shift units 101 to 104 according to delay information I-SEL<1:i> inputted thereto. That is, the delay information I-SEL<1:i> is information which determines the delay value of the delay circuit.
Accordingly, the conventional delay circuit may delay the input signal by various delay values. However, the operation of the delay circuit may be unstable when the input signal is activated at a relatively high frequency.